1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and a memory cell used for the nonvolatile semiconductor memory device, more specifically to a nonvolatile semiconductor memory device having a variable resistive element in which a memory cell can store information in accordance with a change of electrical resistances.
2. Description of the Related Art
At present, an MRAM (Magnetic RAM), OUM (Ovonic Unified Memory), and RRAM (Resistance control nonvolatile Random Access Memory) are present and proposed as nonvolatile memories respectively using a variable resistive element capable of storing information in accordance with a change of electrical resistances. Each of these devices realizes a nonvolatile memory in the form of storing information by changing resistances and reading the information in accordance with a change of the resistance values. For example, the MRAM constitutes a memory cell by using an MTJ (Magnetic Tunnel Junction) device and its contents are disclosed in Japanese Unexamined Patent Publication No. 2002-151661. FIG. 16 shows a configuration of a portion of the memory cell relating to reading. Moreover, a configuration is described in the specification of Japanese Patent Application No. 2002-185234 by the applicant of this application as a memory cell configuration using an RRAM element. FIG. 17 shows the memory cell configuration. Though the memory cells shown in FIGS. 16 and 17 are different from each other in variable resistive element but they are common to each other in that selection transistors serving as a variable resistive element and a selection element respectively are connected in series. In the case of each memory cell, the gate of a selection transistor 3 is connected with a word line WL, one end of a variable resistive element 2 is connected with a bit line BL, the source of the selection transistor 3 is connected with a source line SL, and the other end of the variable resistive element 2 is connected with the drain of the selection transistor 3.
A case of a memory cell using an RRAM element is described below. FIG. 18 shows a memory cell array configuration when using the memory cell in FIG. 17. A memory array (the same meaning as a memory cell array) has a plurality of word lines WL and a plurality of source lines SL and a memory cell at a portion where a bit line BL intersects a word line WL and memory cells are arranged like a matrix. FIGS. 19A and 19B show schematic section views of the memory cell shown in FIG. 18.
The reading operation of the memory array is described below. A bit line selection transistor 4 and a word line driver 6 are controlled so that a memory cell to be read is selected by a bit line BL and a word line WL, and a source line control circuit 7 sets a source line SL connected to the selected memory cell to the ground potential. Under the above conditions, by applying a bias voltage for reading to a selected bit line from a charging circuit of a bit line of a reading circuit 5, a current route is formed in the range from a selection bit line to the RRAM element 2 of a selected memory cell, selection transistor 3, source line SL, and ground potential. The current circulating through the selection bit line is changed depending on the resistance value of the RRAM element 2 of the selected memory cell. The current circulating through the bit line is determined by the reading circuit 5 to output the data stored in the memory cell. FIG. 20 shows an example of a reading circuit for determining the current value. According to the reading circuit in FIG. 20, a load circuit 8 is connected to a bit line BL through the bit line selection transistor 4 to convert a bit line current into a voltage at a connection point N of the bit line selection transistor 4 and the load circuit 8. A current source for generating a reference current for determining each current value corresponding to the data value stored in the memory cell is prepared and a voltage generated by the current source (the voltage is hereafter referred to as a reference voltage Vref) and the voltage converted by the bit line current is determined by a comparator circuit 9 to output the determination result (CPOUT). FIG. 21 schematically shows a load line (straight line) A when using a resistance as the load circuit 8 and current-voltage characteristics B and C of a bit line current corresponding to each binary data.
In the case of the above reading operation, the voltage difference input to the comparator circuit 9 increases as the bit line current difference increases as shown by the graph in FIG. 21. When the voltage difference input to the comparator circuit 9 is large, operations of the comparator circuit 9 are also accelerated. Therefore, to read information from a memory cell at a higher speed and more stably, it is preferable to increase the bit line current difference. In this case, the bit line current is obtained from the total value of resistance values of various portions through which the bit line current circulates, that is, the resistance of the RRAM element 2, on-state resistance of the selection transistor 3, on-state resistance of the bit line selection transistor 4, and wiring resistance (parasitic resistance) of a bit line BL. Therefore, when other resistances are larger than the resistance of the RRAM element 2, the above bit line difference is relatively decreased and a stable reading operation and high-speed operation become difficult.
FIG. 22 shows a simple model of a bit line current route. In FIG. 22, the model is constituted by the selection transistor 3 connected to the RRAM element 2, bit line selection transistor 4 for selecting a plurality of bit lines BL, and a bit line BL. It is enough that the number of bit selection transistors 4 is equal to the number of bit lines in order to select a plurality of bit lines BL. The number of bit selection transistors 4 is smaller than the number of the selection transistor 3 of a memory cell. Therefore, even if the driving capacity of a transistor is increased in order to decrease an on-state resistance, that is, the gate width of the transistor is increased, the influence of increase of the whole area of a memory array is small. Moreover, to decrease the resistance value of a bit line, there is a method of decreasing the wiring material of a bit line in resistance or length. Anyway, this is a problem common to nonvolatile memories. However, the situation is different for the selection transistor 3 in a memory cell. To improve the driving capacity of the selection transistor 3, it is effective to increase the gate width of the above transistor. However, when the transistor is connected to each RRAM element 2, a lot of transistors are required. Therefore, when increasing the gate width, the whole area of a memory array is increased and the manufacturing cost is greatly influenced. As a result, the on-state resistance of the selection transistor 3 is a big factor that the above bit line current difference cannot be increased.